There have conventionally been proposed trench gate type semiconductor devices including trench gate structure as power device-dedicated insulated gate type semiconductor devices. For the conventional trench gate type semiconductor devices in general, high withstand voltage design and low on-resistance design are in trade-off relation.
Patent Document 1, for example, discloses a trench gate type semiconductor device, which pays attention to the above trade-off relation. The trench gate type semiconductor device of Patent Document 1 has structure as schematically shown in FIG. 30. That is, an N+ source region 31 is arranged on upper surface side in FIG. 30 and an N+ drain region 11 is at the bottom side. Between the N+ source region 31 and the N+ drain region 11, there are arranged a P body region 41 and an N− drift region 12 in order from upper side. Furthermore, a part of upper surface side is drilled and a gate trench 21 is formed in the drilled portion. Furthermore, a gate electrode 22 is built in the gate trench 21. Still further, a P floating region 50 is arranged immediately below the gate trench 21. Furthermore, the gate electrode 22 is insulated from a P body region 41 by a gate dielectric 24 formed on wall of the gate trench 21.
In this trench gate type semiconductor device, a depletion layer spreads from a PN junction portion of the P body region 41 and the N− drift region 12 toward the N+ drain region 11 and another depletion layer spreads from a bottom portion of the P floating region 50 toward the N+ drain region 11 when gate voltage is switched OFF. That is, the P floating region 50 promotes to get the N− drift region 12 depleted. Thereby, higher withstand voltage design of a drain-source section can be achieved, according to Patent Document 1.
Furthermore, as another example of a trench gate type semiconductor device, Patent Document 2 discloses of it. In the trench gate type semiconductor device of Patent Document, a P floating region 59 is arranged at a position away from a gate trench 21, as shown in FIG. 31. According to Patent Document 2, the P floating region 59 can realize higher withstand voltage design of a drain-source section, similar to the insulated gate type semiconductor device of FIG. 30.
The semiconductor device of FIG. 31 is manufactured by taking the following process. An N− silicon layer for an N− drift 12 is formed on an N+ substrate which grows in to an N+ drain region 11 by means of epitaxial growth. The N silicon layer is formed up to the level Z shown in FIG. 31. Next, the P floating region 59 is formed by means of ion implantation and the like. Further on, rest portion of the N− silicon layer is formed by means of epitaxial growth again. Thereby, there is thus formed a semiconductor device of which P floating region 59 is fully surrounded with an N− drift region 12 silicon. It is to be noted that by repeating the above process, plural P floating regions 59 different in depth can be formed depths.
Furthermore, a terminal area of the above-mentioned trench gate type semiconductor devices has structure as shown in FIG. 32, in general. That is, there is formed a P terminal diffusion region 61 of which depth is similar or deeper than a gate trench 21, in a terminal area. Thereby, a depletion region spreads from around the P terminal diffusion region 61 to relax concentration of electric field at a terminal area when gate voltage is switched OFF.    [Patent Document 1] JP Laid-open Patent Publication No. 10-98188    [Patent Document 2] JP Laid-open Patent Publication No. 9-191109
However, the semiconductor device of FIG. 30 has had the following problems. That is, the P floating region 50 is formed by means of ion implantation from the bottom portion of the gate trench 21. Therefore, the bottom portion of the gate trench 21 is damaged somewhat. Accordingly, in case the gate dielectric 24 is kept being formed with the gate trench 21 damaged, device characteristics and reliability are likely to lower. Furthermore, the gate electrode 22 faces the P floating region 50. Therefore, charges disperse inside the gate electrode 22, specifically, a portion where the gate electrode 22 faces the P body region 41 and a portion where the gate electrode 22 face the P floating region 50, when gate voltage is switched ON. As a result, on-resistance becomes large.
On the other hand, as to the semiconductor device of FIG. 31, the P floating region 59 is formed away from the gate trench 21. Therefore, higher withstand voltage design can be intended with evading an on-resistance problem. However, at least two times of epitaxial growth process is required to form a P floating region 54 completely surrounded by an N− drift region 12, which takes considerable time to complete.
Furthermore, for relaxing concentration of electric field at a terminal area, there is required process to form a P terminal diffusion region 61 of which thickness differs from thickness of respective P floating regions formed in a cell area. Therefore, the number of manufacturing process is larger and it takes time to complete. Furthermore, since heat load is large, impurity of an N− drift region 12 (epitaxial layer) diffuses and impurity concentration becomes uneven. For compensating the unevenness of impurity concentration, thickness of the N− drift region 12 must be thickened, which results in large on-resistance.
The present invention has been made to resolve at least one of the above-mentioned problems the conventional trench gate type semiconductor devices have had. That is, the present invention intends to provide an insulated gate type semiconductor device and manufacturing method thereof which realize both higher withstand voltage design and lower on-resistance design and can be manufactured simply.